The phenomenon of "clock wander" in synchronous wide area networks (WAN) can cause errors in transmission of digital signals over such networks. Error-free signal transmission over such networks requires that data enter a network node at the same rate as data emerges from the node. If this condition is not satisfied at all network nodes by implementation of an appropriate network synchronization scheme, then some data can be lost.
In the prior art, network synchronization has been implemented by means of "building integrated timing supply" (BITS) clocks, or by Digital Signal 1 ("DS1", formerly "T1") signals consisting of framed all ones. As specified in ITU-T G.703, DS1 signals comprise a 1.544 Mbps time division multiplexed bit stream. More recently, Optical Carrier level N ("OC-N") signals have been used synchronize multiple WAN clocks. OC-N signals are optical signals, with "N" being a multiplier (i.e. N=1, 3, 12, 48, 192, . . . ) applied to a basic 51.84 Mbps optical signal. Ideally, all network clocks are synchronized to a primary reference source (PRS). This is typically achieved via phase locked loop (PLL) methodology.
The performance characteristics of frequency locked loop (FLL) methodologies are relatively poor in comparison to those of PLL methodologies. FLLs use a frequency discriminator to detect loop lock, with a feedback signal being provided to maintain loop lock. The frequency discriminator output level is sufficiently high at higher frequency offsets, but at lower frequency offsets the output level can be so low that it will not suffice to maintain proper loop lock, resulting in "wander" of the synchronization frequency produced by the FLL. For example, the frequency offsets between different network clocks are typically a fraction of 1 Hertz, so a frequency discriminator produces no practically useful output. Phase detectors and PLLs are accordingly preferred in network synchronization methodologies.
Synchronization quality can be defined in accordance with any one of several national or international telecommunication or organizational specifications, such as Bellcore, ITU-T, ANSI, etc. The "wander generation" and "wander transfer" parameters of a clock are defined in terms of "maximum time interval error" (MTIE) and "timing deviation" (TDEV), as will now be explained.
"Wander generation" is a measurement used to quantify the amount of "wander" generated by a clock synchronization circuit. It is well known that digital clocks exhibit pulse position modulation errors. That is, the edges of clock pulse signals output by digital clocks deviate from the ideal clock edge positions. The term "jitter" is used to describe short term signal variations, such as pulse position modulation frequencies which exceed 10 Hz. The term "wander" is used to describe longer term variations of significant digital signal properties (e.g., zero level crossings) from their ideal positions in time, and is applied to pulse position modulation frequencies below 10 Hz. Jitter is typically attributable to additive Gaussian noise, whereas wander is typically attributable to slowly varying environmental conditions.
A variety of different sources can introduce low frequency modulation resulting in wander. These include changes in operating temperature and 1/.function. noise. An oscillator locked to a wander-free reference clock in a narrow bandwidth PLL will exhibit wander above the frequencies at which the open loop gain is below 0 dB. In digital network synchronization, very narrow bandwidth (below 0.1 Hz) PLLs are used to filter accumulated wander from the PRS to generate a timing reference signal. Such clocks must satisfy short term stability requirements and limit the amount of wander which they generate. For example, the Bellcore and ANSI standards stratify clocks according to their long term stability, and limit their short term stability.
"Wander transfer" is a measurement used to quantify the amount of wander that is transferred from a "wandering" input reference to an outgoing OC-N signal. The synchronization reference circuit containing the PLL should filter wander above 0.3 Hz according to the ITU-T G.813 standard.
Optical signal telecommunication systems are characterized by various sources of wander besides those mentioned above. For example, changes in operating temperature cause wander by varying the light propagation characteristics of the optical signal-carrying fiber. A light pulse propagates through a long fiber with a given velocity. If the fiber's index of refraction changes due to temperature variation, the signal propagation velocity through the fiber is also changed. This is mathematically equivalent to a change in the physical length of the fiber (i.e. as though the distance between the signal transmitter and receiver had changed, relative to the transmitter-receiver distance at a different fiber temperature). Consequently, data transmitted into one end of the fiber at one frequency is received at the opposite end of the fiber at a different frequency. The output frequency of the laser which produces the optical signal is also temperature dependent. Further, the propagation delay of light pulses transmitted through the fiber varies as a function of signal wavelength, producing a further frequency differential effect.
As previously explained, jitter is defined in terms of frequencies exceeding 10 Hz, whereas wander is defined in terms of frequencies below 10 Hz. Consequently, jitter and wander are specified in different ways. Jitter is specified in terms of UI (unit interval) RMS or Peak-to-Peak values, but may also be specified in units of time (e.g. nanoseconds) or phase (e.g. degrees). Wander is specified in terms of maximum time interval error (MTIE) and time deviation (TDEV).
MTIE describes the frequency offset of a clock from its ideal frequency, and the phase changes of the clock, over an "observation" period. MTIE is specified in units of nanoseconds of peak-to-peak wander. TDEV describes the spectral content of the clock and is specified in units of RMS nanoseconds of wander.
In order to determine the MTIE and TDEV parameters of a clock, one must measure the clock's time interval error (TIE). TIE is the time difference between an ideal clock and the observed clock, as will now be explained with reference to FIG. 1 in which .DELTA..tau.1, .DELTA..tau.2, . . . represent TIE.
The observation time interval, .tau., can be set to any convenient value (it is independent of clock frequency). At the end of the observation time interval a measure is made of how much the observed imperfect clock has deviated from the ideal clock (the phase difference). Longer observation times should produce larger values of .DELTA..tau.. The MTIE for a particular observation interval is simply the maximum TIE that results from an infinite number of TIE measurements, each performed after particular observation intervals.
By definition, the maximum wander frequency is 10 Hz, so it is possible to completely describe the wander signal up to 10 Hz if the TIE is sampled at twice this rate (the Nyquist rate of 20 Hz; although a higher rate is preferably used to avoid any aliasing). The TIE can be measured and recorded at 50 ms intervals, then by setting different "sliding windows" equal to different observation intervals, the maximum TIE values can be determined by grouping the measured values into the sliding windows. A constant frequency offset will produce the same MTIE value for a given observation period; MTIE will increase linearly with increasing observation time. MTIE is a good metric of frequency offsets between an observed clock and an ideal clock, and also provides a record of any phase transients (i.e. one-shot phase jumps).
MTIE does not reveal how "noisy" the observed clock signal is. The TDEV measurement is used to represent the spectral components of the observed clock. To measure TDEV the same TIE measurements previously collected at 50 ms or faster are used, and digital signal processing (DSP) filtering techniques are applied to quantify the spectral components. As shown in FIG. 2, DSP filtration blocks DC, so frequency offsets are not included in the measurement. Any phase transients that may occur do so rarely and any resulting energy from these transients tends to average out over a large number of samples having the same integration interval values.
Synchronous network clocks are classified according to different "strata". For example, the network master clock is known as the Primary Reference Source (PRS) is classified as Stratum 1. The following table lists the clock stratum of a typical synchronous network.
Clock stratum Typical location(s) 1 Primary Reference Source 2 Class 4 toll office 3 Class 5 end office 4 Channel bank, end user multiplexer
The aforementioned specifications require that a stratified clock have MTIE and TDEV values below predefined masks when the clock is locked to a reference clock. Values of TDEV and MTIE are measured against the reference clock. For example, in the context of the present invention, the aforementioned "masks" are specified by GR-253-CORE or ITU-T G.813 and set maximum allowed MTIE or TDEV for measurements made under specified conditions. A SONET NE optical or electrical output must meet the MTIE and TDEV wander generation requirement masks depicted in FIGS. 3 and 4.
Conformance to this requirement is tested with a wander-free reference having bandlimited white noise phase modulations (jitter) of 1000 ns p--p.
The jitter is bandlimited with 3 dB cut-off frequencies at 10 Hz and 150 Hz. This specification tests the short term stability of the clock source.
The MTIE wander generation specification limits both the frequency offset and phase transient characteristics of the locked clock with respect to the reference clock at all times. The TDEV wander generation specification limits the phase noise of the locked clock for very low frequencies. The wander transfer specification requires that a stratified clock filter out any wander of the reference clock signal above a particular frequency offset, which is typically measured fractions of 1 Hertz. Moreover, the wander transfer specification limits the bandwidth of a phase lock loop to an exceptionally narrow PLL loop bandwidth. Consequently, the PLL's VCXO must have very high free running stability and very good phase noise characteristics (i.e. in order to yield MTIE measurements below FIG. 3 MTIE mask for observation times below 4 sec and TDEV measurements below the FIG. 4 TDEV mask for integration times below 4 sec). It is difficult to reliably satisfy the wander generation and wander transfer specifications using conventional PLL components such as phase detectors and loop filters, primarily because such components are subject to imprecise VCXO control characteristics.
Analog phase detectors can be used, but they tend to be very sensitive to temperature fluctuations. Furthermore, compliance with the aforementioned specifications requires that the synchronization circuitry provide a holdover in the case of an input signal failure ("holdover" is a mode of PLL operation in which last frequency before entry into the holdover mode is maintained). Typically, the synchronization circuitry provides the holdover by storing information about the last good known reference frequency as a digital value. Generally, the information in question is more precisely stored in digital form, as opposed to storage in analog form in a sample and hold circuit, because the information may need to be stored for intervals exceeding 24 hours in accordance with Bellcore GR-253-CORE, Dec. 2, 1995, Issue 2.
If the value representing the last known reference frequency is stored in digital form, with the synchronization circuitry using an analog phase detector, then one must convert the analog voltage output of the phase detector to digital form. This requires an analog-to-digital converter (ADC). It can thus be seen that if an analog phase detector is used, the synchronization circuitry requires two additional analog circuits, both of which are susceptible to temperature fluctuations. The bandwidth of the synchronization circuitry is very narrow, namely less than 1 Hertz in order to filter wander on the incoming reference clock signal, according to the aforementioned specifications. Temperature fluctuations can cause variations in the transfer characteristics of the phase detector, ADC, and DAC. The PLL's narrow bandwidth response characteristics may not be fast enough to compensate for variations in transfer characteristics of the phase detector and ADC, resulting in wander. To avoid such wander, it is preferable to minimize the use of analog circuitry susceptible to temperature fluctuations, and instead use a phase detector having a digital output.
One example of a prior art phase detector capable of producing the desired digital output is a counter with a latch (FIG. 6). Such phase detector circuits typically consist of an N-length counter clocked by the VCXO frequency, as depicted in FIG. 6. Usually, the VCXO frequency of a simple PLL like that depicted in FIG. 5 is a multiple of the reference clock frequency. But, the clock signals compared by the phase detector must have the same (or very close) frequencies. A Divide-by-M circuit is accordingly provided in the feedback path of the FIG. 5 PLL to divide the VCXO frequency down to be the same as a reference clock frequency. The FIG. 6 modified phase detector does not require the synchronization reference and VCXO clock signals to have the same frequency, so a Divide-by-M circuit is not necessary. The counter shown in the FIG. 6 circuit can be designed to have a period equal to period of the synchronization reference signal, thus providing function equivalence to the Divide-by-M circuit of FIG. 5.
The FIG. 6 phase detector produces a digital output value proportional to the phase difference between the VCXO frequency and the synchronization reference frequency. Although it not as sensitive to temperature variations as an analog phase detector, the FIG. 6 phase detector nevertheless has a serious drawback. Specifically, the FIG. 6 phase detector can not distinguish finer phase increments than those defined by the VCXO time intervals. Therefore, this type of phase detector exhibits a so-called "dead band": the phase of the synchronization reference can vary within one VCXO timing interval without being detected. Similarly, the phase of the VCXO can vary within one VCXO timing interval without producing a change in the phase detector's output value. If the VCXO timing interval is of the same order as the allowances permitted by the MTIE and TDEV specifications, then the synchronization PLL may create more wander than the specifications permit. A higher VCXO frequency can be used to reduce the dead band, but this requires an additional PLL to multiply the VCXO frequency several times.
The present invention addresses the aforementioned digital phase detector dead band wander generation problem. The value of the counter is sampled at certain reference instances and used to control the frequency of the VCXO. The invention provides a method which is superior in performance and more robust than the analog phase detector method, is more efficient than standard techniques for increasing clock frequency, and meets the wander and jitter related specifications of Bellcore GR-253-CORE and ITU-T G.813.